This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-095310, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device for reducing the pulse width of an input pulse.
2. Description of the Related Art
A conventional pulse width changing circuit for changing the pulse width uses a logic gate circuit in order to change a pulse width used in a circuit system. Examples of the pulse width changing circuit are shown in FIGS. 13A, 13B, 14A, and 14B.
FIG. 13A is a circuit diagram showing a circuit for reducing an input pulse width, and FIG. 13B is a waveform chart showing its operation. FIG. 14A is a circuit diagram showing a circuit for widening an input pulse width, and FIG. 14B is a waveform chart showing its operation.
The circuit shown in FIG. 13A is comprised of a delay circuit 101 and AND gate 102. In general, the delay circuit 101 is made up of an even number of inverter circuits 103. The amount of a delay d of the delay circuit 101 is an integer multiple of the gate delay amount of the inverter circuit 103.
As for the operation, as shown in FIG. 13B, the two inputs of the AND gate 102 change to xe2x80x9c1xe2x80x9d the delay d of the delay circuit 101 after an input xe2x80x9cinxe2x80x9d changes from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d. An output xe2x80x9coutxe2x80x9d changes to xe2x80x9c1xe2x80x9d upon the lapse of the gate delay amount of the AND gate 102.
Then, the input xe2x80x9cinxe2x80x9d returns from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, and the output xe2x80x9coutxe2x80x9d returns to xe2x80x9c0xe2x80x9d upon the lapse of the gate delay amount of the AND gate 102.
In the circuit shown in FIG. 13A, the leading edge of the pulse delays by the delay d of the delay circuit 101, so that the pulse width of the input xe2x80x9cinxe2x80x9d can be reduced by the delay d.
The circuit shown in FIG. 14A comprises a delay circuit 101 identical to that of FIG. 13A, and an OR gate 104.
As for the operation, as shown in FIG. 14B, the input xe2x80x9cinxe2x80x9d changes from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d, and then one input of the OR gate 104 changes to xe2x80x9c1xe2x80x9d. The output xe2x80x9coutxe2x80x9d changes to xe2x80x9c1xe2x80x9d upon the lapse of the gate delay amount of the OR gate 104.
The input xe2x80x9cinxe2x80x9d returns from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, and the two inputs of the OR gate 104 change to xe2x80x9c0xe2x80x9d upon the lapse of the delay d of the delay circuit 101. The output xe2x80x9coutxe2x80x9d returns to xe2x80x9c0xe2x80x9d after the lapse of the gate delay amount of the OR gate 104.
In the circuit shown in FIG. 14A, the trailing edge of the pulse delays by the delay d of the delay circuit 101, so that the pulse width of an input pulse can be widened by the delay d.
A conventional circuit for reducing a long input pulse is shown in FIGS. 15A and 15B.
As shown in FIG. 15A, this circuit is constituted by cascade-connecting circuits shown in FIG. 13A, and each circuit reduces the pulse width by the delay d of the delay circuit 101. Various pulse widths can therefore be formed from an input pulse by extracting a pulse from an arbitrary position. FIG. 15B shows output pulses at respective nodes (NODE0 to NODE2) together with the delay state.
The conventional circuits shown in FIGS. 13A, 13B, 14A, 14B, 15A, and 15B are effective only for an input pulse with a pulse width larger than the delay d of the delay circuit 101. In addition, the amount of the delay d is equal to or larger than the gate delay amount of the logic gate circuit such as the inverter circuit 103.
In principle, the conventional circuit cannot slightly reduce the pulse width by an amount smaller than the delay d of the delay circuit 101, i.e., cannot reduce the pulse width by an amount smaller than the gate delay amount of the logic gate circuit.
Since the conventional circuit is configured by a combination of an AND or OR gate and a delay circuit 101 including a plurality of logic gate circuits, it requires a large number of circuit elements and is bulky. This inhibits an increase in the integration degree of a semiconductor integrated circuit device and reduction in chip area.
A semiconductor integrated circuit device according to a first aspect of the present invention comprises: a plurality of MIS transistors, each of the MIS transistors having a gate including a circuit element represented by an equivalent circuit in which a capacitance and a resistance are parallel-connected; and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors.
A pulse width changing circuit according to a second aspect of the present invention comprises: cascade-connected logic gate circuits, wherein the pulse width changing circuit reduces a pulse width by an amount smaller than a gate delay amount of the logic gate circuit.